The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials, design, and fabrication tools have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. As semiconductor devices scale down, the ability to control device performance metrics such as leakage while maintaining manufacturable processes for a planar type transistor becomes difficult. One advance undertaken by the semiconductor industry is the development of multi-gate (e.g., dual-gate) transistors. Some of these devices may be known as fin-type field effect transistors (FinFETs) when their structure includes a thin “fin” extending from a substrate. A typical FinFET is fabricated on a substrate with an overlying insulating layer with a thin ‘fin’ extending from the substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. A double gate is beneficial in that it allows for gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow.
In the course of these advances, efforts have been made to develop fabrication methods to realize the desire for smaller feature sizes. For example, methods have been developed that reduce the pitch of features on a substrate without changing the photolithography technology used. Double Patterning Lithography (DPL) techniques are such methods. One such method is forming spacers on a sacrificial line features. However, there are disadvantages to this and other conventional method, for example, variations in the spacer structures (e.g., sidewalls), challenges with etching the line features, and maintaining etch selectivity between line features, spacers, and/or other layers formed on the substrate. Thus, while the present methods are suitable for some intended purposes, benefits would be gained from improved fabrication methods.